Samsung zHBM: The Next Leap in AI Memory, Explained

tech Aug 8, 2026 8 min read By Pyae Phyo Kyaw

On 5 August 2026, at the Future of Memory and Storage (FMS) conference in Santa Clara, California, Samsung Electronics unveiled zHBM — a next-generation 3D memory architecture that stacks high-bandwidth memory vertically on top of AI accelerators instead of placing it beside them. The company claims the design delivers roughly 8x the performance, more than 10x the density, and 3x the power efficiency of HBM5, the memory generation expected to follow today's HBM4 [1][2]. Kim Kyung-ryun, a vice president in Samsung's DRAM development division, closed the keynote with three words: "Samsung is back" [1]. The announcement landed at a moment when memory is the hottest bottleneck in AI hardware — and when Samsung is fighting to overtake SK hynix, the current HBM leader, in a market growing faster than any other part of the chip industry [6][7]. This post explains what zHBM is, why it matters, and what it means for the rivalry that now defines the AI hardware market.

Figure 1: The zHBM story at a glance — from the FMS 2026 reveal to the memory race ahead.

What is zHBM?

High-bandwidth memory (HBM) is the workhorse of AI accelerators. It is a stack of DRAM dies connected by vertical through-silicon vias and mounted on a logic base die, delivering terabytes of bandwidth per second to the GPU or accelerator beside it. Each generation roughly doubles the interface: HBM3 moved to a 1024-bit bus, and today's HBM4, standardized by JEDEC, doubles bandwidth to about 2 TB/s per stack with a 2048-bit interface [6]. HBM5, the next step, is expected to push further — and it is the baseline Samsung chose for its zHBM claims [1][3].

zHBM changes the geometry. Instead of sitting next to the accelerator on the package, zHBM is stacked directly on top of it, using the vertical (Z) axis — hence the name. That shortens the distance data must travel between compute and memory, attacking the "memory wall" that has become the defining bottleneck of AI hardware [6]. Samsung says the architecture also supports customer-specific IP in the interlayer between memory and the accelerator, letting chip designers tune capacity and performance for their own workloads [2][4]. The trade-off is physics: stacking memory on top of a processor concentrates heat in one place, which is why Samsung paired the design with a new heat-dissipation structure and GAA transistors that draw less power [1][2].

The numbers behind the claim

Table 1: Samsung's zHBM claims versus HBM5, as presented at FMS 2026.
Metric	zHBM claim vs HBM5	Source
Performance	~8x	[1][2]
Memory density	>10x	[1][2]
Power efficiency	~3x	[1][2]
Thermal resistance	>50% lower	[1][2]

Why now: the memory wall

The reason zHBM matters is a widening gap between compute and memory. According to TrendForce, AI model computing power has grown 3x in two years, while memory bandwidth has grown only 1.6x — meaning most AI workloads are now limited by how fast data can be fed to the processor, not by the processor itself [6].

That imbalance has turned memory into the hottest commodity in tech. HBM demand grew more than 130% year over year in 2025 and is projected to grow more than 70% in 2026, while DRAM prices are forecast to rise more than 70% this year [6]. The shortage is so acute that TrendForce says no single supplier can meet total demand for Nvidia's Rubin platform [8]. The memory supercycle has been building for two years: suppliers have moved to multi-year take-or-pay contracts, and HBM operating margins now exceed those of Nvidia and TSMC — a sign of how much pricing power the three memory makers hold [6].

Table 2: The memory wall in numbers. Source: TrendForce.
Metric	Value
AI compute growth, past 2 years	3x
Memory bandwidth growth, past 2 years	1.6x
HBM demand growth, 2025	>130% YoY
HBM demand growth, 2026 (projected)	>70% YoY
DRAM price rise, 2026 (projected)	>70%

Who: Samsung vs SK hynix

zHBM is as much a competitive statement as a technical one. Samsung lost the HBM crown to SK hynix during the HBM3 era and has spent two years clawing it back. The market share numbers tell the story [7][9]:

Table 3: HBM market share by supplier. Sources: Counterpoint via TechSpot and Seoul Economic Daily.
Supplier	Q3 2025	Q1 2026
SK hynix	53%	58%
Samsung	35%	21%
Micron	11%	—

SK hynix still leads, holding 58% of the HBM market in Q1 2026 and winning two-thirds — possibly more than 70% — of Nvidia's HBM4 orders for the Vera Rubin platform [9][10]. But Samsung has momentum: it shipped the industry's first mass-produced HBM4 to Nvidia in February 2026 at 11.7 Gbps, and its HBM revenue is projected to nearly triple to about 25 trillion won (~$17.6 billion) in 2026 [7][8]. Nvidia is reportedly planning a "dual-bin" approach for its Rubin accelerators, with Samsung's faster HBM4 in a premium tier and SK hynix's in the mainstream tier [8].

zHBM is Samsung's bet that the next generation — HBM5 and beyond — will be won on architecture, not just yield. As one industry official told The Korea Herald, "performance requirements for memory are becoming more critical than production yield" [8].

When and where: FMS 2026

zHBM was one of several announcements at FMS 2026, held 4–6 August in Santa Clara [1][2]. Samsung also showed:

zNAND-O — a next-generation NAND for on-device AI, in 4- and 8-layer versions. Samsung says that running a 120-billion-parameter GPT model, it matched DRAM token-processing speed at one-sixth the operating cost [1][5].
V10 BV-NAND — the industry's first 10th-generation V-NAND with more than 400 layers, using wafer bonding to deliver roughly 58% higher density than V9 [1][2][4].
HBM4E samples — shipped to customers in May 2026, following HBM4 mass production in February [2].

How it works: stacking, bonding, and new transistors

Three technologies underpin zHBM. First, advanced wafer bonding — the same technique behind V10 BV-NAND — which lets Samsung fuse memory and logic layers without the bulky interconnects of conventional packaging [2][3][4]. Second, GAA (gate-all-around) transistors in HBM for the first time, built on a 2nm-class foundry process, which cuts power and heat at the memory level [1]. Third, a new heat-dissipation structure that lowers thermal resistance by more than half — critical when you are stacking hot memory directly on top of an even hotter accelerator [1][2].

Tom's Hardware notes the claims are impressive but somewhat vague — Samsung has not specified exactly what "8x performance" refers to, nor when zHBM will ship [3]. Comparisons to HBM5 suggest a late-2020s or early-2030s arrival [3].

The historical parallel: 3D NAND, 2013

There is a direct precedent for this bet. In 2013, Samsung introduced V-NAND, the industry's first 3D NAND flash, stacking 24 layers of memory cells vertically when the planar (2D) approach was hitting physical limits [11]. Skeptics questioned the cost and complexity; within a few years, 3D NAND became the industry standard and every major manufacturer followed. zHBM is the same play in a different arena: when a horizontal approach runs out of room, go vertical. The difference is that this time the stakes are the entire AI infrastructure build-out, and the competitor — SK hynix — is not a follower but a leader defending its position [7][9][10].

What next: the road to HBM5

Three things to watch. First, the HBM4E ramp: SK hynix is already shipping 12-layer, 48GB HBM4E samples at 16 Gbps — 30% faster than HBM4, with more than 20% better energy efficiency and 17% lower thermal resistance — for Nvidia's Rubin Ultra, and Samsung is matching with its own HBM4E samples [2][9]. Second, whether zHBM moves from concept to silicon: wafer bonding at scale, thermal management, and customer-specific interlayers are all unproven at production volumes [3]. Third, the packaging bottleneck: stacking memory on accelerators will demand even more advanced packaging capacity, the same constraint that has already made TSMC's CoWoS a chokepoint [6].

If zHBM delivers even half of what Samsung claims, it would reset the HBM competitive order — and "Samsung is back" would stop being a slogan and start being a market share chart [1][7].